Capacitors with high energy storage density and low esr

ABSTRACT

Electrostatic capacitors with high capacitance density and high-energy storage are implemented over conventional electrolytic capacitor anode substrates using highly conformal contact layers deposited by atomic layer deposition. Capacitor films that are suitable for energy storage, electrical and electronics circuits, and for integration onto PC boards endure long lifetime and high-temperature operation range.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a Divisional of U.S. patent application Ser. No.11/658,201 filed on Jan. 19, 2007, which is a National Stage of PCTApplication No. PCT/US2005/025768 filed on Jul. 20, 2005, which PCTapplication claims the benefit of U.S. Provisional Application No.60/590,748 filed Jul. 23, 2004. All of the above patent applications,provisional, PCT, and non-provisional, are hereby incorporated byreference to the same extent as though fully contained herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the area of electronic components and morespecifically to apparatus and method for constructing capacitors withhigh capacitance and high-energy storage density as well as lowequivalent series resistance.

2. Description of Prior Art

Capacitor devices have a host of applications in the electrical,electronics, and microelectronics arts. Many different usefulimplementations of capacitors were successfully implemented andcommercialized. Capacitor properties such as capacitance density,operating voltage, energy storage density, equivalent series resistance(ESR), temperature resilience, and lifetime were constantly improved.Concurrently, substantial drive to reduce the cost and the size ofcapacitors drove the technology into substantially automaticmanufacturing methods and achieved satisfactory commodity status formost applications.

Capacitors are useful for energy storage wherein benefits are fastresponse, compatibility with high voltage, and extended charge/dischargecycle lifetime (compared to batteries). Most suitable for energy storageand other power applications are electrolytic capacitors that achieverelatively high capacitance density by combining the benefit of a higharea anode and corresponding high dielectric constant insulating layerwith the contact properties of a liquid or solid electrolyte cathode.The technology of electrolytic capacitors is well known in the art andmany useful devices are currently implemented and available in themarket. One particular useful design, named Aluminum electrolyticcapacitor, applies high area etched aluminum foil with typically between×25 to ×100 area enhancement factor as an anode and implements thedielectric layer by anodic oxidation growth of Al₂O₃ layer. The cathodeis implemented with additional aluminum foil and the contact between thecathode and the dielectric is typically facilitated by the usage of anelectrolytic solution.

Effective incorporation of aluminum electrolytic capacitors into compactdevices typically involves winding strips of anode/dielectric foils anda cathode foil separated with a strip of paper or other films suitablefor electrolyte impregination into a compact tubular shape followed byimpregination with a suitable electrolyte to facilitate the cathodecontact.

Aluminum electrolytic capacitors are most commonly used in the industrywith advantageous high-capacitance density, relatively high voltagecompatibility, and extremely low cost. However, a relatively shortlifetime in the order of only several thousands of hours at 85° C.,relatively high and constantly deteriorating ESR, high leakage current,polarity, and limited temperature range are only some of the undesiredcharacteristics that have limited the applicability of aluminumelectrolytic capacitors, as well as tantalum electrolytic capacitors, asenergy storage devices or otherwise circuit components in highperformance and highly-reliable electronics. Recent improvements tobasic electrolytic capacitor technology successfully incorporate solidpolymer electrolytic contact to enhance the lifetime and the usefultemperature range with advantageously lower ESR. Clearly, the weak linkof aluminum capacitor technology relates to the electrolytic nature ofthe contact.

Electrolytic capacitors, in general, have been most useful to attainhigh-capacitance density while they fell short of achieving satisfactorylong lifetime, high-voltage compatibility, extended temperature range,and low ESR. In contrast, the technology of thin film capacitorstypically implements metalized polymer thin films in an electrostaticcapacitor design to achieve significantly suitable high-voltagecompatibility, long lifetime, alternating current (AC) compatibility,and improved high-temperature resilience. Thin film capacitors areeconomically mass-produced by coating both sides of a polymer film withthin metallic films, typically using physical vapor depositiontechniques. Compact thin film capacitors are implemented by windingstrips of the metalized polymer films into tubular shaped bodies.Alternatively, multilayer stacks of metalized polymer films have beenimplemented with substantially reduced ESR for the entire capacitor.These film capacitors excel at the high voltage and AC-performance endbut have been limited, so far, to relatively low-capacitance density.Additionally, the mainly implemented polymer dielectric films areinherently limited to the temperature range below 120° C. withimplications for lower reliability at high-power applications.

The high-capacitance density of electrolytic capacitors is mainlyattributed to the starting substrate with its related high-capacitancearea. Additionally, a dielectric constant of anodized Al₂O₃ within analuminum electrolytic capacitor or an anodized Ta₂O₅ within Taelectrolytic capacitors at ∈_(r)˜8 and ∈_(r)˜25, respectively, farexceed the typical dielectric constant of ∈_(r)˜2 for suitable polymerfilms. The capacitance follows the formula:

$\begin{matrix}{C = \frac{ɛ_{r}ɛ_{0}A}{d}} & (1)\end{matrix}$

wherein ∈₀ is the permittivity of vacuum, ∈_(r) is the relativedielectric constant of the dielectric material, A is the effective areaof the capacitor, and d is the thickness of the dielectric layer.Practically, the thickness of the dielectric layer is determined by thespecifications of the voltage that can be reliably applied over thecapacitor without causing catastrophic breakdown or deterioration ofelectrical properties over the lifetime of the capacitor. For example,d=V/E_(DB) where E_(DB) is the dielectric breakdown field of thedielectric layer. In practice, capacitors are typically derated toensure extended lifetime, and the dielectric thickness is typicallyextended by a factor of ×1.5-×2.

A schematic layout of aluminum electrolytic capacitor is depicted inFIG. 1. Accordingly capacitor 100 is fabricated by winding a stack offoils 150 into a compact roll with tubular shape. The foils are slitinto long strips prior to the winding process. Foils stack 150 includesanode aluminum foil 102 with etched high-area surface 103 and an Al₂O₃dielectric layer 104 formed by an anodic oxidation process. Cathodealuminum foil 106 includes a thin layer of Al₂O₃ 108, which is typicallysubstantially thinner than the thickness of dielectric layer 104. Thesurface of cathode foil 106 is enhanced by etching typically to a muchless extent than the area enhancement 103 of anode foil 102. A paperfoil 110 is inserted between the anode and the cathode foils prior towinding the capacitors. Foil 110 is soaked with electrolyte solutionfollowing the winding, and a cathode contact is formed by electrolytesolution penetrating into gaps 112 and 114 between foil 110 and anode102 and foil 110 and cathode 106, respectively. Clearly, capacitor ESRrelates with the consistency of the electrolyte solution within gaps 112and 114. The capacitor essentially consists of an equivalent circuit oftwo capacitors connected in series with the larger capacitor formed onthe anode and the smaller capacitor formed on the cathode. Thesecapacitors are mainly suitable for direct current (DC) applicationswhere voltage polarity is substantially maintained positive at theanode.

Electrolytic capacitors typically exhibit continuous deterioration ofESR corresponding to the deterioration of the electrolytic cathodecontact. Post fabrication yield improvement relies on the electrolyticsolution to further anodize dielectric defects to repair locally crackedand thinned dielectric by the growth of anodic oxide at the localizeddefect. This growth is enhanced at the defect due to a substantiallylocalized higher current.

Capacitors with a capacitance value typically in the range of 0.01-1 μFare employed in significant numbers on a typical PC board (PCB) tocreate useful electrical and electronic circuits and, therefore, occupya significant portion of the PCB area. Additionally, costs related todiscrete capacitors assembly over the PCB, as well as yield reductionand failure sometimes related to several hundreds of solder joints, aresubstantial. Finally, performance limitations related to capacitors toPCB contact resistance and inductance are sometimes difficult toovercome. Accordingly, the electronic industry has pursued theintegration of capacitors into capacitor arrays and most recently intothe layout of the actual PCBs. Full integration of capacitors into thePCB may advantageously reduce the area that is occupied by thecapacitor, further reducing the size of electronic devices. Significantcost and weight reductions are additional benefits. Additionally,performance limitations related to contact resistance and inductance arealso foreseen as greatly reduced by this integration.

However, the down sides to integrated capacitors are clearly andobviously the high level of PCB customization that is required and thepossible PCB yield reduction relating to defective capacitors. Whilecustomization is not foreseen as an issue given the inevitable migrationof PCBs into full customization, the industry seeks integrationtechniques that are compatible with current PCB fabrication technologyand that are quickly and easily configurable upon the need to constantlyupdate and advance consumer-electronics products, sometimes within onlyseveral months. Integrated capacitors yield, therefore, must be as closeas possible to 100% and/or some capacitor redundancy is necessary tosupport low-cost PCB manufacturing and reduce the insurmountable cost ofPCB testing.

There is a need for capacitors with improved energy retention densityhaving both high-capacitance density and high-voltage compatibilitywhile maintaining low ESR. These capacitors should preferably have anextended lifetime at an extended temperature range. Additionally, thereis a need to improve the performance and extend the lifetime ofhigh-capacity capacitors and increase the specific capacitance pervolume and weight. Also necessary are methods that enable capacitorintegration into the layout of PC boards without significantly alteringcurrent fabrication techniques while maintaining the ability of existingPC board fabrication lines to quickly and effectively customize theirproduct. In particular, low-cost capacitor device layouts and relatedfabrication methods are desired.

SUMMARY OF THE INVENTION

Atomic layer deposition (ALD) has emerged as a possible depositionmethod in integrated circuit thin film applications. It has up to nownot been considered for macroscopic applications, such as electrolyticcapacitors. ALD, up to now, has been considered too slow a process tomake the fifty-micron thick films generally associated with suchapplications. ALD is a cyclic process carried out by dividing aconventional CVD process into an iterated sequence of self-terminatingprocess steps. An ALD cycle contains several (at least two) chemicaldose steps in which reactive chemicals are separately delivered into theprocess chamber. Each dose step is typically followed by an inert gaspurge step that eliminates the reactive chemicals from the process spaceprior to introducing the next precursor. In this manner, ALD lays downfilms, one atomic layer by another. Thus, to build up a fifty-micronfilm using this technique has been considered far too laborious and slowfor commercial purposes.

However, ALD also provides robust and atomic-level control of filmthickness and properties without the need for in-situ monitoring. Itdeposits continuous and uniform films on any three-dimensional surfacestructure, penetrating the most narrow and deep grooves, vias, andcavities. Accordingly, ALD films have unique pinhole free and low stressproperties which may render them ideal candidates for high yieldfabrication of high area devices.

In recent years, there has been a significant drive to insert AtomicLayer Deposition (ALD) films into semiconductor manufacturing. In thenext decade, the critical size of an integrated circuit will scale downto only 10 to 25 atomic layers. Consequently, atomic-level control offilm thickness and properties is necessary. ALD grows films in a uniquelayer-by-layer fashion allowing for conformal and uniform growth overchallenging substrate topologies with atomic-level control and iscurrently the only known film deposition technique proven to accomplishsuch stringent requirements. Therefore, ALD holds an important key tothe future of the IC industry, as well as many other technologies.

Within the ALD process, the deposition thickness per cycle is preciselyand reproducibly dictated by self-saturation mechanism. The depositionis the outcome of chemical reactions between reactive molecularprecursors and the substrate. In similarity to CVD, elements composingthe film are delivered as molecular precursors. The net reaction mustdeposit the pure desired film and eliminate the “extra” atoms thatcompose the molecular precursors. In the case of CVD, the molecularprecursors are fed simultaneously into the CVD reactor. The substrate iskept at a temperature that is optimized to promote chemical reactionbetween the molecular precursors concurrent with efficient desorption ofbyproducts (so that the byproducts do not incorporate into the film).Consequently, the reaction proceeds to deposit the desired pure film.Table 1 summarizes the main differences between the ALD and CVDprocesses.

TABLE 1.1 Comparison between ALD and CVD CVD, PVD ALD Growth ModeContinuous Stepwise - layer by layer Growth Rate Variable Growth perstep is accurately defined Thickness Control Rate X Time Dialed in witha selected number of steps Growth Initiation Nucleation, grainContinuous film growth Film Properties Pinholes, Pinhole-free,negligible stress compressive stress Conformality Varies and difficult100% and robust over toughest to maintain 3D structures

ALD offers many advantages over other more conventional techniques andis best suitable for some of the most challenging thin film depositionapplications. ALD films can be uniquely grown continuously on substratesavoiding inferior discontinuous transition caused by nucleation. As aresult, ALD films grow pinhole free and practically stress free. Allother deposition techniques initiate film growth by nucleation.Nucleation is the outcome of only partial bonding between the substrateand the growing film. In the CVD case, for example, molecular precursorsattach to the surface mainly by CVD reactions between the reactiveprecursors on the surface. Nucleation is followed by the growth ofgrains. When the grains finally coalesce into continuous films, thethickness could be on the order of 5 nm to 10 nm in the case of CVD andeven thicker in the case of physical vapor deposition (PVD). Filmsinitiated by nucleation exhibit substantial compressive stress andabundance of pinholes that extend far beyond coalescence depth. Pinholesand compressive stress are associated with non-ideal grain boundariesand typically render CVD and PVD films inadequate for passivation andencapsulation applications at layer thicknesses of less than 500 nm.

ALD films can grow continuously at any thickness, provided that thesurface of the substrate is made reactive to one of the ALD precursors.In this case, ALD films can be grown with layer-by-layer continuity allthe way from the interface. The ability to initiate the surface andstart layer-by-layer growth from the first layer makes ALD filmscontinuous, low stress, and pinhole free; thus, it is an ideal candidatefor devices with high-capacitance area substrates wherein thereliability and yield crucially depend on the number or density ofdefects. For example, ALD dielectric films are developed for DRAMcapacitor applications wherein they were proven to maintain close to100% yield for ultrathin films in the range of ˜5 nm over area-enhancedwafers with actual area exceeding 10,000 cm². Additionally, Al₂O₃dielectric films predominantly overtook PVD films in the magnetic datastorage industry wherein magnetic sensors are manufactured atpractically 100% yield using ALD. Finally, ALD films utilized for deviceencapsulation applications have shown significant device reliabilityimprovements indicating pin-hole free coatings over large-size flatpanel devices, as well as other devices. As a result, very thinencapsulation films can be realized by ALD with minimized adverse impacton device performance. For example, IC devices can be encapsulated atthe wafer level with minimized impact on performance or subsequentpackaging process flow.

Given the superior low-defectivity and conformality of ALD films, theyare exceptionally suitable for the deposition of dielectric andconductive films for high-energy and capacitance applications.

It is the objective of the present invention to provide a method forcapacitor manufacturing with improved capacitance and energy densitywhile maintaining low ESR. It is another objective of the invention toimprove electrolytic capacitor device layouts and create anelectrostatic capacitor device layout by substituting the electrolytewith a highly conformal conductive film, therefore constructing anelectrostatic capacitor while mainly implementing electrolyticcapacitors manufacturing techniques. It is yet another objective of thisinvention to improve the temperature resilience and the lifetime ofhigh-capacitance and high-energy density capacitors. It is also theobjective of this invention to provide a capacitor device layout andrelated fabrication methods that are compatible with alternating current(AC). It is also an objective of this invention to provide capacitorsthat can be integrated into PC boards.

In another scope of the invention, capacitor manufacturing yield isimproved by incorporating methods and apparatus for repairing defectswithin capacitor dielectric layers. In another aspect of the invention,capacitor manufacturing yield is further improved by incorporating“self-healing” of localized, low-dielectric, breakdown spots.

In another aspect of this invention, the equivalent series resistance(ESR) of high-capacitance and high-energy density capacitors issubstantially reduced by substantially reducing the contact resistancewith both the anode and the cathode.

The invention implements high-capacitance area anode substrates that arecommonly used in the fabrication of electrolytic capacitors togetherwith conformal formation of high-quality dielectric films and conductivefilms to fabricate electrostatic capacitors with substantially improvedcapacitance density, lifetime, and temperature endurance.Complimentarily, the invention teaches layouts and fabrication methodsthat achieve high-capacitance density and high-energy density capacitorswith extremely low ESR. Additionally, the invention presents a viablescheme for capacitor-PCB integration.

Methods that are useful to repair defects in capacitor dielectric layersinclude ALD deposition into imperfections, utilization of ALD films forat least a portion of the dielectric layer, and biasing the dielectriclayers under oxidizing conditions. Additionally, the entire capacitorfoil stack is biased to substantially remove a conductive contact filmfrom weak points by virtue of localized heat generation and evaporationand/or oxidation of the contact layer from the weak points.

In one aspect of the invention, a capacitor comprises a capacitor foil.The capacitor foil includes a metallic foil. The metallic foil ischemically etched to achieve high-capacitance area. The capacitor foilfurther includes a conformal and substantially uniform dielectric layergrown over the metallic foil and a substantially uniform and conformalconductive film grown on the dielectric layer. In another aspect of theinvention, the capacitor preferably includes an additional metal foilthat preferably forms a substantial electrical contact with a portion ofthe conformal conductive film. In another aspect of the invention, atleast a portion of the conformal conductive film is preferably grown byALD. In another preferred aspect of the invention, the capacitor foilpreferably comprises an additional conductive layer preferably havingsubstantial electrical contact with the conformal conductive film.Preferably, the capacitor further includes an additional metal foil andthe additional metal foil preferably forms a substantial electricalcontact with a portion of the additional conductive film. In anotherpreferred aspect of the invention, the capacitor foil is preferablyformed into a strip, the additional metal foil is preferably formed intoa strip, and the strips preferably have substantially similar width andlength; and the strip of capacitor foil and the strip of additionalmetal foil are preferably wound to form a substantially compactcapacitor core shape. In one additional aspect taught by the invention,electrical contacts are preferably formed on the planar faces of thecapacitor core. The electrical contacts preferably comprise a firstinsulation over the edge of the additional metal foil on the first face,a first electrical contact with the edge of the metal foil preferablyformed on the first face, a second insulation over the edge of the metalfoil on the second face, and a second electrical contact with the edgeof the additional metal foil preferably formed on the second face. Inanother aspect of the invention, the electrical contacts are preferablyformed on the planar faces of the capacitor core preferably including afirst insulation over the edge of the additional conductive layer on thefirst face, a first electrical contact with the edge of the metal foilpreferably formed on the first face, a second insulation over the edgeof the metal foil on the second face, and a second electrical contactwith the edge of the additional conductive layer preferably formed onthe second face. In another preferred aspect of the invention, thecapacitor foil is preferably formed into a strip and preferably wound toform a substantially compact capacitor core shape. In an additionalaspect of the invention, the capacitor preferably comprises a capacitorcore stack comprising a first metal foil and a repeatable stack. Therepeatable stack preferably comprises a selected number of foil pairs,and each foil pair preferably includes the capacitor foil and theadditional metal foil. In an additional aspect of the invention, thecapacitor preferably comprises a capacitor core stack of the capacitorfoil. Further, the capacitor core stack is preferably cut into capacitorcore pieces, and electrical contacts are preferably formed on twoparallel sides of the capacitor core pieces. These electrical contactspreferably comprise a first insulation over the edge of the additionalmetal foil on the first side, a first electrical contact with the edgeof the metal foil formed on the first side, a second insulation over theedge of the metal foil on the second side, and a second electricalcontact with the edge of the additional metal foil formed on the secondside. In another preferred variant of the invention, the capacitor corestack is preferably cut into capacitor core pieces, and electricalcontacts are preferably formed on two parallel sides of the capacitorcore pieces. The electrical contacts preferably comprise a firstinsulation over the edge of the additional conductive layer on the firstside, a first electrical contact with the edge of the metal foilpreferably formed on the first side, a second insulation over the edgeof the metal foil on the second side, and a second electrical contactwith the edge of the additional conductive layer preferably formed onthe second side. In a preferred aspect of the invention, at least aportion of the dielectric layer is preferably formed by ALD. In anotherpreferred aspect of the invention, at least a portion of the dielectriclayer is preferably formed by anodic oxidation. In an additionalpreferred modification of the invention, a portion of the dielectriclayer is preferably formed by anodic oxidation, a portion of thedielectric layer is preferably formed by ALD, and the thickness of theALD portion is preferably selected to substantially increase thebreakdown voltage of the dielectric layer. In one preferred aspect ofthe invention, the capacitor foil is preferably electrically biasedwherein electrically biased preferably comprises applying electricalpotential between the metal foil and the conformal conductive film, andthe electrical potential is preferably selected to increase thebreakdown voltage of the dielectric layer without substantially reducingthe capacitance of the capacitor foil. In an additional aspect of theinvention, the capacitor foil is preferably electrically biased whereinelectrically biased preferably comprises applying electrical potentialbetween the metal foil and the conformal conductive film, and theelectrical potential is preferably selected to reduce the leakagecurrent through the dielectric layer without substantially reducing thecapacitance of the capacitor foil. In another preferred aspect of theinvention, the dielectric layer is preferably electrically biasedwherein electrically biased preferably comprises applying electricalpotential between the metal foil and an electrolyte, the electrolytepreferably provides electrical contact with the dielectric layer, andthe electrical potential is preferably selected to increase thebreakdown voltage of the dielectric layer without substantiallyincreasing the thickness of the dielectric layer. In an additionalaspect of the invention, a preferred application of the capacitor foilis mounted onto a PCB and the PCB comprises electrical contact pads. Themounting preferably comprises substantially making low ESR electricalcontact with the electrical contact pads, and the capacitor foil is thenpreferably delineated to define capacitors. The defined capacitorspreferably comprise a selected capacitance, and the selected capacitanceis preferably determined by the capacitance per area of the capacitorfoil and the area of the defined capacitors. Preferably, the integratedcapacitors are embedded within the layer structure of the PCB. Apreferred material for the metal foil according to one aspect of theinvention comprises aluminum. A preferred material for the dielectriclayer according to one aspect of the invention comprises aluminum oxide.A preferred material for the conformal conductive film comprisestitanium nitride. In a preferred aspect of the invention, thehigh-capacitance area of the metal foil comprises more than 10× areaenhancement. In another preferred aspect of the invention, the capacitorfoil preferably comprises the high-capacitance area on both sides, andthe dielectric layer is preferably grown on both sides of the metalfoil, and the conformal conductive film is preferably grown on thedielectric layer on both sides of the capacitor foil.

The invention also teaches a capacitor fabrication method comprisingapplying high-capacitance area metal foil, subsequently oxidizing theentire area of the high-capacitance area foil and conformally growing aconductive film onto the dielectric film to facilitate a capacitor foil.Preferably, the method further comprises winding the capacitor foil intoa capacitor core, and the capacitor core has two faces, electricallycontacting to the edge of the high-capacitance area metal foil on thefirst face and electrically contacting to the edge of the conductivefilm on the second face. In a preferred variant of the invention, thecapacitor fabrication method further includes stacking the capacitorfoil into a capacitor core stack, cutting the capacitor core stack intocapacitor core pieces, selecting two parallel sides on the capacitorcore pieces, electrically contacting to the edge of the high-capacitancearea metal foil on the first side, and electrically contacting to theedge of the conductive film on the second side.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part ofthe specification, illustrate the preferred embodiment of the presentinvention, and together with the description serve to explain theprinciples of the invention. In the drawings:

FIG. 1 depicts schematically the prior art layout of aluminumelectrolytic capacitors;

FIG. 2 depicts schematically the layout of high-energy storage densitycapacitors according to the invention;

FIGS. 3 a and 3 b depict schematically the mechanism for defect repairimplementing deposition of ALD dielectric films over dielectric filmsgrown by anodic oxidation according to the invention;

FIGS. 4 a and 4 b depict a cross-sectional SEM image of a structureseamlessly filled with an ALD film according to the invention;

FIGS. 5 a-5 e depict schematically the mechanism of gap filling with ALDaccording to the invention;

FIGS. 6 a and 6 b depict schematically the layout of high-energy storagedensity capacitors utilizing a thick cathode film or a thick depositedoverlaying film to reduce ESR according to the invention;

FIGS. 7 a and 7 b depict schematically the layout of high-energy storagedensity capacitors utilizing a displaced cathode foil to reduce ESRfollowing the winding of a cathode foil with an anode-dielectric-contactfoil according to the invention;

FIGS. 8 a-8 d depict schematically the fabrication of low resistancecontact with the anode and cathode according to the invention;

FIG. 9 depicts schematically a cross-sectional view of a completedcapacitor according to the invention;

FIGS. 10 a-10 c depict schematically the fabrication of low-resistancecontact with the anode and cathode according to the invention;

FIG. 11 depicts schematically a mulilayer stacked capacitor layoutaccording to the invention;

FIG. 12 depicts schematically a mulilayer stacked capacitor layoutaccording to the invention;

FIG. 13 depicts schematically the layout of a discrete capacitormanufactured from a single layer of stacked capacitor foil according tothe invention;

FIG. 14 depicts schematically the layout of a PCB integrated capacitoraccording to the invention; and

FIGS. 15 a and 15 b depict schematically a high-energy storage capacitoraccording to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A. Area EnhancedElectrostatic Capacitors

A key aspect of the invention is the fabrication of macroscopicelectrical devices, such as macroscopic capacitors using conformallayers deposited using atomic layer deposition (ALD). These devices canbe used as discrete electrical components, as components of hybridcircuits, as portions of integrated circuit boards, and otherapplications. In this disclosure, “macroscopic” means the individualelectrical element, such as an individual capacitor, is 200 microns insize or larger. Preferably, the individual electrical element is 2,000microns or larger.

In an exemplary preferred embodiment of the invention, an etchedaluminum foil is applied as the starting substrate. Commerciallyavailable etched aluminum foils are mass-produced for applications aselectrolytic capacitors anodes as known in the art. These foils areavailable, for example, from 25 μm and 250 μm with specific areaenhancement up to ˜×100. FIG. 2 illustrates the capacitor 200 composedof etched aluminum foil 202, dielectric layer 204, and contact layer 206making electrical contact 210 with cathode aluminum foil 208. A varietyof etched aluminum foils may be implemented as anode 202 with areaenhancement in the range of from ×25 to ×100. The high-capacitance areasubstrates are characterized by a fine etch structure that is mostsuitable for implementation of relatively thin dielectric layer 204 inthe range of from 10 nm to 200 nm and, therefore, are suitable for lowvoltage capacitor applications in the range of from 5V to 100V. Lowerarea enhancement is suitable for thicker dielectric films in the rangefrom 0.2 μm to 2 μm (and even thicker) and accordingly higher voltagecapacitor applications in the range of from 100V to 1000V.

The characteristic area enhancement of foil 202 is selected to best fitthe properties of the capacitor. For example, foil 202 is implemented byusing conventional aluminum foil with 50 μm thickness and ×40 areaenhancement that typically exhibits a consistent etch pattern thatextends from 10 μm to 25 μm deep into the foil from both sides. Theetched structure consists of deep pores ranging in width between 2 μmand 4 μm penetrating substantially vertically from the foil's surface.The density of foil 202 is reduced by the etching down to ˜1.5grams/cm³. Dielectric layer 204 is preferably formed by anodic oxidationas known in the art. Other methods suitable for forming dielectric layer204 with improved yield are discussed below, including growth of highlyconformal film using Atomic Layer Deposition (ALD) or combinations ofanodic oxidation and complementary ALD grown films. The contact layer206 is formed using ALD to create a conformal electrode over dielectriclayer 204. As detailed above, ALD is most suitable for the deposition ofhighly conformal high-quality films over high-capacitance areasubstrates. For example, a 50 nm TiN film with resistivity of ˜300 μΩ cmis suitable. Alternatively, a stack of 5 nm TiN and 45 nm W isimplemented with resistivity of ˜10 μΩ cm to improve ESR through bettercontact resistance.

Capacitor 200 is formed by winding strips 250 cut from foil 202 (nowcoated with layers 204 and 206) together with an un-etched capacitorgrade aluminum foil 208 to form a layered substantially tubular shape.Foil 208 typically has ˜5 μm thickness and 2.7 grams/cm³ density. Thelayered structure is shown in a schematic cross-sectional view in theinset of FIG. 2. The contact between foil 208 and layer 206 typicallyincludes only a portion of the area 210. A portion of the area 212corresponding to the porous extension into the etched pores does notdirectly contact foil 208. Nevertheless, the contact resistance into thepores is relatively small as detailed below.

In a specific example of FIG. 2, a strip of 2 cm×500 cm of foil 202 isapplied with 1 μm of dielectric Al₂O₃ layer 204. The area enhancementincludes a ×40 enhanced surface area and the utilization of both sidesof the foil to generate ˜80,000 cm² of actual area. This capacitor has C˜566 μF of capacitance and is suitable for 500V applications when 50%derating is used. Alternatively, a 10V capacitor is formed with a ×100enhanced foil 202 and a 20 nm thick dielectric layer 204. Strips with 2mm×10 cm area have an actual area of ˜400 cm² given the area enhancementand the applicability of both sides of foil 202. This capacitor has acapacitance value of C ˜140 μF which is substantial given the smallvolume of ˜0.025 cm³ (˜3 mm diameter when rolled over a 1/16″outerdiameter Teflon rod) and the weight of ˜0.02 grams. Accordingly,capacitance density of ˜7000 μF/gram is achieved.

B. Yield Improvement Methods

Electrolytic aluminum capacitors typically fail when capacitor ESRdeteriorates beyond useful range. Dielectric failure is typicallyprevented by a self-healing mechanism attributed to the electrochemicalformation of dielectric layer thickening at weak spots. Weak spots canbe described as a localized thin dielectric area that relates toimperfections in the anodic oxidation process. For example, FIG. 3 aillustrates schematically localized thin spot 222 formed withindielectric layer 220. Cracks and other defects such as 222 areunavoidable in the anodic oxidation process due to significant (morethan ×1.4 at room temperature) expansion of aluminum upon oxidation andthe fact that the Al₂O₃ grown in the anodic oxidation process is growingat the interface between the substrate aluminum and the layer Al₂O₃ andunder already formed Al₂O₃, therefore significantly stressing theoverlaying, already formed Al₂O₃. The localized thin spots aresusceptible to dielectric breakdown at substantially lower voltage thanthe fully thick areas of layer 220. Accordingly, when electrolyticcapacitors are subjected to the fully specified voltage, the localizedthin spots break down and exert relatively high current that islocalized at the breakdown spots. The current induces additional anodicoxidation that essentially “repairs” the spots by the growth of thicklocalized Al₂O₃. The repair process ceases when the dielectric breakdownis turned “off”; that is, when the dielectric thickness at that spotreaches an appropriate thickness. This useful mechanism of “aging” is akey advantage of electrolytic capacitor technology, enabling thefabrication of large capacitance capacitors with high yield. However,the “self-correction” mechanism relies on the electrolyte to supply theoxygen for the oxidation process.

In the electrostatic capacitor layout disclosed in this invention, theelectrolytic solution is replaced with solid conductive film 206 (FIG.2) and the final capacitor does not posses the “self-correction”properties. However, implementation of anodic oxidation techniques toform dielectric layer 204 is still desired in most cases. Accordingly,the embodiment shown in FIG. 3 b implements a stack of anodized Al₂O₃layer 220 with an ALD Al₂O₃ layer 224 to provide defect repair by virtueof conformally filling ALD film 226 into localized thin spot 222 duringthe creation of layer 224. When the width of the localized defect isless than half of the thickness of layer 224, the ALD technique isproven to seamlessly fill the feature 222 up to the total thickness ofcombined layer 220+224 as illustrated in FIG. 3 b.

FIG. 4 illustrates a SEM image (FIG. 4 a) of a 400 nm thick ALD film22+24+26 deposited over a complicated device structure. The devicelayout prior to deposition includes crevices 18 and 20, as well as atrench feature 12 that is substantially narrow than 2×400 nm. FIG. 4 bprovides an illustration of the layout of FIG. 4 a for better clarity.The ALD film is also divided in FIG. 4 b into three “layers” toillustrate the consecutive growth and fill-up of feature 12. Note theconsistent and seamless filling of features 18 and 20, the undesiredcrevices that relate to some delamination of metal features 4 and 6,respectively, during the metalization process. Also note that feature12, although not a defect but rather a designed feature, is completelyand seamlessly filled up with the ALD film. Also, the ALD film exhibitsprecisely 400 nm thickness in all areas that do not correspond tofeatures narrower than 800 nm wherein the completely conformal film didnot manage to completely fill up the features. This fact is explicitlyobvious at feature 16 that is only slightly wider than 800 nm and,therefore, is perfectly conformally coated but not closed.

As illustrated in FIG. 4, when the thickness of layer 22+24+26 exceedshalf of the width of a crevice or a feature, for example area 12, thefeature (or defect) is entirely filled and the thickness of the ALDlayer above the crevice minus the depth of the crevice equals thethickness of layer 22+24+26 on the entire area. This seamlessgap-filling property is attributed to the layer-by-layer growthmechanism of ALD and is further illustrated in FIG. 5.

In FIG. 5 a, a recess 67 has been formed in layer 66. As shown in FIG. 5b, an initial layer of dielectric film 70 is grown over the entiresurface area of the device layout by ALD. The use of ALD enables a layerof dielectric film 70 to completely cover the surface area of theexisting structure, including recess 67. The thickness of dielectricfilm 70 is grown through the successive deposition of additional layersof dielectric film. As shown schematically in FIG. 5 c, dielectric film70′ is grown to a thickness of slightly less than the width of recess67. It will be appreciated by one of average skill in the art that thelayer-by-layer deposition of dielectric film 70′ is schematicallyillustrated in the figures by the dashed lines that separate dielectricfilm 70′ into a layered structure. However, it will further beappreciated that, due to the conformal nature of ALD films, in practicedielectric film 70′ forms a single seamless, conformal film, regardlessof the number of discrete layers of dielectric material deposited toform dielectric film 70′.

As shown in FIG. 5 d, dielectric film 70″ is eventually grown to athickness that seamlessly closes recess 67. Accordingly, it will beappreciated that dielectric film 70″ is grown to a thickness that isequal to approximately half the width of the recess, or approximatelyhalf the thickness of device layer 66 to form plug 72. A closure,therefore, forms between the portions of dielectric film 70″ that coverseach side of the recess. The position of the closure is represented byarrow 82. Subsequent layers of dielectric material may be furtherdeposited on the surface of dielectric film 70″. After recess 67 hasbeen filled, each such successive layer will be conformally deposited toform an additional thickness over the entire area of the existingdielectric film 70″′, as shown in FIG. 5 e.

As localized defects are relatively small, relatively thin over-layer224 (FIG. 3 b) is necessary to “repair” the anodized layer 220. Forexample, a layer 224 in the thickness range of from 10 nm to 50 nm issuitable for most applications. Accordingly, the 500V capacitor in theexample given above with a dielectric thickness of 1 μm is substantiallyproduced with an anodized Al₂O₃ dielectric layer that is complemented bya thin over-layer of ALD Al₂O₃ film. A combination of 950 nm to 990 nmand 5 nm to 10 nm of anodized and ALD Al₂O₃ layers, respectively, arerecommended. In contrast, in the above example for a 10V capacitor withonly 20 nm of dielectric film, it is suitably useful to implement theentire dielectric film with ALD.

In some applications, the implementation of ALD films for the formationof the entire dielectric layer may be preferred even for high-voltagecapacitors. These include the fabrication of capacitors over substratesmade from material other than aluminum such as etched nickel foils,pressed powder substrates, or capacitors made with higher dielectricconstant dielectric layers such as Ta₂O₅, HfO₂, ZrO₂, TiO₂ andcombinations of these layers, and aluminum oxide or silicon dioxide inthe form of alloys and/or nano-laminates as known to those who areskilled in the art of ALD. For example, a capacitor for very hightemperature applications is formed over nickel foil using Al₂O₃ ALD filmto implement the dielectric layer. In another example, a 1:3 layer ofAl₂O₃:Ta₂O₅ ALD alloy is implemented over an etched aluminum foilsubstrate with advantageous combination of high dielectric constant of∈_(r)˜16 and high dielectric strength of ˜7 MV/cm to enable ˜×1.4 highercapacitance×voltage density. The alloys and nano-laminate techniquesknown in the art of ALD are also proven to produce extremely low-defectdensity films of otherwise inferior materials. For example, 1:1 alloyingof TiO₂ with Ta₂O₅ is useful to produce high-quality amorphousdielectric layers with ∈_(r)˜32 and breakdown voltage of >5 MV/cm givinga ×2 enhanced capacitance density over Al₂O₃ dielectric.

The advantages of low-cost anodic oxidation, defect elimination andincreased capacitance density can be obtained by implementing acombination such as 50 nm of anodized Al₂O₃ and 100 nm of combinationhigh-dielectric constant ALD film such as TiO₂/Ta₂O₅ with advantageous50V rating and 1600 μF/gram capacitance density when implemented overaluminum foils with ˜×75 area enhancement, as compared with only 760μF/gram for an equivalent capacitor with 100 nm of Al₂O₃ dielectric.

In another preferred embodiment of the invention, defects in an anodizedAl₂O₃ layer are repaired by an electrolytic aging process. Accordingly,the anodized foil, such as 202+204 in FIG. 2, is sandwiched between twoelectrolytic paper foils and metal plates serving as the cathode.Contact is made to foil 202 serving as the anode. The stack is immersedwithin an electrolytic solution to resemble a two-sided planarelectrolytic capacitor and DC voltage is applied to perform the “aging”process as known in the art of electrolytic capacitor fabrication, onlythe “aging” is performed soon after the dielectric “forming” (the anodicoxidation) step rather than over the complete capacitor. Following the“defect repair”, foil 202+204 is rinsed to remove the electrolyte.

In similarity to self-healing of metallized thin film capacitors, arather thin electrode film is locally heated at defect points by thehigh-localized current to locally evaporate the metallic electrode andthe weak spot and therefore isolate the weak spots from the capacitor.Accordingly, film 202 (FIG. 2) including layers 204 and 206 are clampedbetween two large plates that are grounded and serve as cathodes. Whenfoil 202 is electrically connected to a DC power source, the thin layer206 can be locally heated at a defect failure point due to high currentand locally eliminate or oxidize layer 206 at the weak spot to provide“self-healing”.

C. Low ESR Capacitors

A major object of this invention is to achieve low equivalent seriesresistance (ESR) capacitors. Layer 206 (FIG. 2) implementations withtypically a thin layer of ALD TiN or other conductive ALD films aremostly suitable to obtain low-contact resistance into the area enhancedfeatures. Typically, a 50 nm layer of TiN ALD film with only 60Ω/□ issufficient to provide low contact resistance into the high area featureswith 0.5 μm-4 μm width and up to 20 μm depth. For example, ˜1 μΩ of ESRis applied to a 10 cm² area capacitor of completed layer stack202+204+206 having ˜×40 area enhancement and ˜20 μm deep etchedfeatures. Likewise, a 5/45 nm TiN/W stack layer 206 will contribute only0.13 μΩ of ESR per the capacitor described above. Accordingly, thecontribution of the contact layer to ESR is not substantial. Embodimentsthat reduce the contact resistance of the entire capacitor areillustrated schematically in FIGS. 6 a and 6 b. FIG. 6 a illustratesconformal conductive film 406 that is formed over dielectric layer 404within the capacitor layout 400. Film 406 makes contact 420 with foil408 across the area of foil 408. To improve contact 420, the nativeoxides are preferably removed from foil 408 prior to winding with foil402 (having the layer stack 404+406 on it). For example, aluminum foil408 is etched in dilute phosphoric acid solution. Alternatively, inlow-temperature capacitor applications, a layer of conductive epoxy orpaste (not shown) is inserted between foil 408 and layer 406. Furtherreduced contact 420 resistance implements thin conductive non-oxidizinglayer (not shown) over foil 406 such as evaporated gold, preferably, inthe thickness range of from 20 nm to 50 nm. Improved contact 420 is alsopreferably achieved by coating the top surface of layer 406 with thinnon-oxidizing film (not shown) such as gold without ambient exposure tosubstantially avoiding contact deterioration from the oxidation of thetop surface of layer 406. Alternatively, materials such as ruthenium(Ru) deposited over foil 408 and/or film 406 reduce contact resistanceby virtue of their conductive oxides, i.e., RuO₂ that may form on thesurface of Ru without substantially increasing the ESR. Layersimplemented to reduce contact 420 resistance do not need to conform tothe high-capacitance area points, since the contact 420 is formed onlyat the top facing surfaces. Accordingly, conventional physical vapordeposition (PVD) techniques are suitable.

While the capacitor layout described in reference to FIG. 6 a issuitable for low ESR applications, further improvements are obtained bythe implementation of thick overlaying films in contact with layer 406.This embodiment further reduces series resistance related to thenon-contact fraction of the area 424. The embodiment 450 is illustratedin FIG. 6 b. Film 458 is preferably formed over contact layer 406′without ambient exposure to avoid surface oxidation of layer 406′. Forexample, layer 458 is formed by sputtering 0.5 μm to 1 μm of aluminum asknown to those who are skilled in the art. While this technique achievessubstantially higher contact area through fractional area 424′, it isnot required to substantially penetrate into the deep high-capacitancearea features such as 422′. In some embodiments, film 458 completelyreplaces foil 408 (FIG. 6 a). In most common applications, relativelythin film 458 is implemented with or without a complementarynon-oxidizing film at the top to improve the contact with foil 408 (notshown). In another example, film 406′ composes metals such as copper orruthenium as seed layers for electroplated copper or nickel film 458. Inthis case, advanced electroplating techniques known to those who areskilled in the art of semiconductor and other device processing areimplemented to substantially refill into features 422′ and furtherreduce the ESR. In yet another embodiment, film 406′ is implementedusing ALD of, i.e., TiN or TiN/W while the seed layer for electroplatingis implemented using sputtering or evaporation, preferably withoutambient exposure. In that case, a seed copper, nickel, or Ru film doesnot need to conform to the entire structure of features 422′. Theelectroplated 458 film creates contact that extends into features 422′to the extent that the seed layer is able to penetrate into thehigh-aspect ratio features. Nevertheless, the PVD-seed/electroplatingmethod described herein is useful to obtain low ESR that is suitable forextremely low ESR applications such as high-peak power energy-storagecapacitors. An electroless plating process is also useful to createlayer 458 over a conductive seed layer.

In an additional preferred embodiment of the invention, layer 458 isdeposited as a continuation of contact layer 406′ using the ALD process.Layer 458 can be made from substantially the same material as layer 406′or from a substantially different material. In another embodiment, layer458 is deposited using suitable CVD processes and suitable conductivematerials such as tungsten (W). Preferably, layer 458 is depositedfollowing the deposition of layer 406′ without ambient exposure. In yetanother preferred embodiment, capacitors for relatively low temperatureapplications are fabricated with a layer of conductive epoxy or pastethat replaces layer 458 (not shown). In this implementation, theconductive material at the appropriate viscosity is applied over layer406′ as known in the art. Application is achieved, for example, byspraying, painting, dipping, or rolling and is preferably applied inmultiple applications using suitably lower viscosity to establish lowresistivity contact over layer 406′ followed preferably by higherviscosity applications to establish a thicker layer 458.

Following the fabrication process, the capacitor film stack includingsubstrate foil 402 (FIG. 6 b), dielectric layer 404, contact layer 406,and conductive layer 458 is slit into strips having suitable length andwidth that accommodate the desired capacitance. The foil is then woundinto a substantially compact shape to fabricate compact and robustcapacitors. Alternatively, the strip of capacitor film stack 252 (FIG. 7a) is wound with strip 208′ to fabricate compact and robust capacitorswith substantially lower ESR configuration. Film stack 252 may or maynot include layer 458. Preferably, capacitor 200′ is fabricated withstrip 252 and strip 208′ slightly offset as illustrated schematically inFIG. 7 a and in the cross-section shown in more detail in FIG. 7 b. Thisoffset winding process creates gaps 254 and edges 256 on the lower 251and upper 253 faces of the tubular capacitor, respectively. Asillustrated schematically in the cross-section of FIG. 7 b, thecapacitor includes alternating foil 202′, dielectric layer 204′, contactlayer 206′, and foil 208′. Alternatively, the capacitor also includeslayer 458 as per the description above in reference to FIG. 6 b (notshown).

Following the winding, the lower face 251 is etched to substantiallyremove layer 206″ (FIG. 8 a) from the exposed area in gaps 254′.Preferably, layer 206″ is over-etched to create recesses 260.Alternatively, if layer 458 was applied as detailed above in referenceto FIG. 6 b, layer 458 is also etched from gaps 254′ and preferablyrecessed using over-etch techniques as known in the art of semiconductorand other device processing (not shown). Preferably, layer 206″ andlayer 458 are etched in solution using suitable selective etchingtechniques as known to those who are skilled in the art. For example,EDTA-H₂O₂—NH₄OH is used to selectively etch TiN without impacting Al₂O₃dielectric layer 204″ or many other dielectric materials implementedwithin layer 204″ over aluminum foil 202″ as known in the art. Inanother example, tungsten in layer 458 can be selectively etched usinghydrogen-peroxide solutions without significantly etching TiN, Al₂O₃, oraluminum as known in the art. The art of wet-etching provides manydifferent and suitable selective etching methods that are adequate forthe creation of process step 200″ (FIG. 8 a) showing only thecross-sectional view of the layers. In process step 200″, only the lowerface 251′ of the capacitor is exposed to the etching media, while theupper face 253′ is prevented from contact with the etching media.Preferably, the rolled capacitors are partially dipped into the etchingmedia to maintain face 253′ unexposed. Alternatively, face 253′ can beprotected within a fixture or by a removable film, and the entirecapacitor may be exposed to the etching media.

In process step 200″′ illustrated in FIG. 8 b, the capacitor is coatedwith a thick insulating layer. FIG. 8 b illustrates the portions 262 and264 of the insulating layers at the bottom 251′ and the top 253′ facesof the capacitor, respectively. However, the insulating layer preferablycoats the entire capacitor. Preferably, layer 262-264 is applied inmultiple applications using dipping or spraying methods with lowerviscosity solution applied first to substantially penetrate into thegaps 254′ and recesses 260, as well as coat over edges 256′ of foil 208″followed by the application of higher viscosity solution to fabricatesubstantially thicker layers and further followed by appropriatebake-out and/or curing of the layer as known in the art. Layer 262-264is selected to suit the performance specifications of the capacitor andspecifically the appropriate temperature range. For example, variousepoxy materials are suitable for low temperature ranging up to ˜100° C.,while polyimide films are suitable for capacitors with temperaturespecifications ranging up to ˜350° C. (for example, Photoneece®PWDC-1000 from Dow Corning). Higher temperature ranges are accommodatedby coating materials such as BCESQ or other equivalent spin-on glassmaterials wherein the temperature range is extended to ˜500° C.Alternatively, layer 262-264 can be deposited using CVD or PE-CVD asknown in the art to preferably fabricate capacitors with and extendedtemperature range exceeding 500° C. (care should be taken in that caseto ensure that other construction materials are also suitable for thehigh temperature range. For example, replacing aluminum with nickel isrequired to extend the temperature range beyond 400° C.). While layer262-264 preferably should substantially penetrate into gaps 254′ andcoat over edges 256′, it is not required to be perfectly conformal andcould include voids at recesses 260 and other hard-to-reach cornerswithout impacting the reliability and the manufacturing yield of thecapacitor. The insulating layer 262-264 is applied to insulate the edgeof foil 202″ and foil 208″ from the contact layers that are formed atthe top face 253′ and the bottom face 251′, respectively, duringsubsequent fabrication step 200″″′ described below in reference to FIG.8 d.

In subsequent process step 200″″ illustrated in FIG. 8 c, the capacitorfaces 251″ and 253″ are polished and subsequently cleaned from debris asknown in the art. Bottom face 251″ is polished to remove a portion ofinsulating layer 262 and a portion of foil 202″ leaving insulating plugs266 between dielectric layer edges 204″′ and exposing foil 202″ edges202″′. The bottom of foil 208″ and layer 206″ are, therefore,encapsulated by the combination of dielectric layer 204″′ and plugs 266.Also, top face 253″ is polished to remove a portion of insulating layer264 and a portion of foil 208″ leaving insulating plugs 268 between foil208″ edges 208″′ and exposing foil 208″ edges 208″′. The top of foil202″, therefore, is encapsulated by plugs 268. Similar polishing anddebris removal techniques are successfully and cost-effectively appliedfor the fabrication of semiconductor interconnect layouts as known inthe art of semiconductor manufacturing. Preferably, capacitor polishingand subsequent debris cleanup is applied to a large number of capacitorsthat are preferably clamped together to create a large, 300 mm diameterarea that enables the utilization of readily available polishingequipment commonly used for semiconductor fabrication. This equipment istypically capable of “dry-in-dry-out” handling of substrates wherein theentire polishing and cleanup is automatically and reproduciblyperformed. Additionally, chemical-mechanical polishing (CMP) methods asknown in the art are used to improve the yield of process step 200″′ bysubstantially matching the erosion rate of the various materials beingpolished. Process step 200″″ preferably implements polishing to achieveplanarized faces 251″ and 253″ that are advantageous for makingelectrical contacts. However, those who are skilled in the art mayimplement other techniques, such as etchback, to fabricate the faces251″ and 253″.

In subsequent process step 200 (FIG. 8 d), electrical contacts 270 and272 are formed over bottom face 251″ and top face 253″, respectively.Contact layers 270 and 272 are substantially connected to the entireedge of foils 202″″ and the entire edge of foil 208″″, respectively, forsubstantially reduced ESR. Contact layers 270 and 272 can be formedusing many different techniques that are known in the art. For example,conductive epoxy is used to make capacitors for low-temperatureapplications. A variety of brazing alloys and brazing techniques aresuitable to fabricate contact layers 270 and 272 making capacitors thatare suitable for high-temperature applications. Swaging techniques, aswell as utilization of conductive epoxies, cements, and pastes, are alsosuitable to form low-resistance contacts with the exposed edges of foils202″″ and 208″″. The preferred embodiment layout that is illustrated inFIG. 8 d achieves very low ESR by substantially contacting to the entireedges of foil 202″″ and foil 208″″ at the bottom face 251″′ and the topface 253″′, respectively, while maintaining high fabrication yield andhigh reliability given the encapsulation of foil 208″″ and foil 202″″ atthe bottom face 251″′ and the top face 253″′, respectively, using plugs266′ and dielectric layer 204″″ and using plugs 268′, respectively. Thiscombination of parallel-like contacts and substantially encapsulatinginsulations is key for the performance, fabrication yield, andreliability of the capacitors fabricated according to the invention.

In further processing, the capacitors are completed by attaching contactpads and encapsulating the capacitors with protective jackets ascommonly known in the art. For example, FIG. 9 illustrates a schematiccross-sectional view of a completed capacitor including contact pads 274and 276 making contact with contact layers 270′ and 272′, respectivelyand further including jacket 278.

In an additional embodiment discussed above in reference to FIG. 6 b,the capacitor layout does not include foil 208′ (FIG. 7 a), and theimproved low ESR contact is derived by a thick contact layer 458 (FIG. 6b). Accordingly, the capacitors are formed by winding only one foil thatincludes (FIG. 10 a cross-sectional view) substrate foil 602, dielectriclayer 604, contact layer 606, and thick contact layer 458′. Preferably,layer 458′ is made from a material that is different from foil 602 tofacilitate useful etch selectivity. In the subsequent process step 600illustrated in FIG. 10 a, the layers 606 and 458′ are selectively etchedat the bottom face 651 to create gaps 654 and undercuts 660. Top face653 then is subjected to a selective etch process 600′ that isillustrated in FIG. 10 b to selectively etch foil 602 and create gaps686. In subsequent process steps, the capacitor is encapsulated andpolished similarly to the process steps described in reference to FIGS.8 b and 8 c above to generate layout 600″ illustrated in FIG. 10 c.Accordingly, the capacitor is prepared for low ESR contact formation byencapsulating layer 458′ and foil 602 with plugs 666 and 668,respectively, at the capacitor bottom face 651 and the capacitor topface 653, respectively, and exposing the edges 688 and 690,respectively, of foil 602 and layer 458′, respectively, at bottom face651 and top face 653, respectively. In subsequent processing, contactlayers and pads and capacitor completion is fabricated similarly to theprocess layout described above in reference to FIG. 8 d and FIG. 9.

Alternative capacitor layouts and related fabrication processes utilizemultilayer stacking techniques. Multilayer stacking techniques areparticularly suitable to fabricate capacitors with relatively smallcapacitance. For example, FIG. 11 illustrates the cross-sectional viewof a multilayer stack made of foil 702, dielectric layer 704, contactlayer 706, and thick layer 758 stacked together multiple times. Forexample, five layers are stacked to create a capacitance area density of354 μF/cm² suitable for 10V applications (with 50% derating) using a 50μm thick foil 702 etched to obtain ×100 area enhancement, 20 nm thickAl₂O₃ dielectric layer 704 on both sides, 50 nm thick TiN contact layer706 on both sides, and 100 nm tungsten layer 758 on both sides, having atotal thickness of ˜0.25 mm. Following the stacking process, thecapacitors are cut into small area pieces such as 1.4×2 mm capacitorshaving 10 μF capacitance and 0.02-0.03Ω ESR. The exemplary capacitorwith ˜70 μFV/cm³ (after encapsulation) represents about a factor of 10improvement over prior art best achieved with tantalum electrolyticcapacitors. This improvement is particularly advantageous given theanticipated significantly better performance, lifetime, and temperatureendurance of the inherently electrostatic capacitors. The multilayerstack is preferably prepared over a large-capacitance area foil andconsequently cut into the small size capacitors. The cutting is followedby removal of debris from the edges using suitable cleaning techniquesknown in the art of semiconductor and other device processing such asmegasonic enhanced etching. In subsequent processing steps that aresubstantially similar to the processing steps described above inreference to FIGS. 10 a-10 c, 8 b, and 8 d, the capacitor layout 700that is illustrated schematically in FIG. 11 is formed. Accordingly, thecapacitor is prepared for low ESR contact formation by encapsulatinglayers 758 and foils 702 with plugs 766 and 768, respectively, at thecapacitor first face 751 and the capacitor second face 753,respectively, and exposing the edges 788 and 790, respectively, of foils702 and layers 758, respectively, at first face 751 and second face 753,respectively and subsequently creating first contact layer 792 andsecond contact layer 794, respectively. In subsequent processing,contact pads and capacitor completion is fabricated similarly to theprocess layout described above in reference to FIG. 9.

Alternatively, multilayer stacking techniques are also implemented withadditional foils 708 to further reduce ESR as illustrated in FIG. 12. Inthe specific example 700′ of FIG. 12, the capacitor does not includecontact improving layers 758 between foils 708 and contact layers 706′.However, these layers and additional oxide suppression layers aresuitable for this implementation in accordance with the descriptiongiven above. Multilayer stacking techniques are particularly suitable tofabricate capacitors with relatively small capacitance. In the exampleof FIG. 12, a cross-sectional view of a multilayer stack made of foil702′, dielectric layer 704′, contact layer 706′, and foil 708 stackedtogether multiple times is depicted. For example, five layers arestacked to create a capacitance area density of 354 μF/cm² suitable for10V applications (with 50% derating) using a 50 μm thick foil 702′etched to obtain ×100 area enhancement, 20 nm thick Al₂O₃ dielectriclayer 704′ on both sides, 50 nm thick TiN contact layer 706′ on bothsides, and 5.8 μm aluminum foil 708 on both sides, having a totalthickness of ˜0.31 mm. Following the stacking process, the capacitorsare cut into small area pieces such as 1.4×2 mm capacitors having 10 μFcapacitance (˜55 μFV/cm³) and ˜10⁻⁴Ω ESR. The cutting is followed byremoval of debris from the edges using suitable cleaning techniquesknown in the art of semiconductor and other device processing such asmegasonic enhanced etching. In subsequent processing steps that aresubstantially similar to the processing steps described above inreference to FIGS. 8 a-8 d, the capacitor layout 700′ that isillustrated schematically in FIG. 12 is formed. Accordingly, thecapacitor is prepared for low ESR contact formation by encapsulatingfoils 708′ and foils 702′ with plugs 766′ and 768′, respectively, at thecapacitor first face 751′ and the capacitor second face 753′,respectively, and exposing the edges 788′ and 790′, respectively, offoils 702′ and foils 708′, respectively, at first face 751′ and secondface 753′, respectively, and subsequently creating first contact layer792′ and second contact layer 794′, respectively. In subsequentprocessing, contact pads and capacitor completion is fabricatedsimilarly to the process layout described above in reference to FIG. 9,and the final dimension of the capacitors are 1.6×2.2×0.5 mm×mm×mm.

Alternative multilayer stacking techniques are implemented by modifyingthe process described in reference to FIG. 8 a, wherein layer 706′ isnot etched to be removed from gap area 766′. Rather, laser scribing isused to remove a narrow lane of layer 706′, such that the edge of thelayer contacts the first contact layer 792′, but is electricallyisolated from the rest of layer 706′ that lies substantially beyond thede-metallized lane. Laser scribing use in stacked layers metallized thinfilm capacitor manufacturing is known in the art and described, forexample, in U.S. Pat. No. 5,055,965 issued Oct. 8, 1991 to Charles C.Rayburn.

Multiple other techniques are useful to fabricate low ESR capacitorswith parallel connection configuration based on techniques known in themacroscopic capacitor art or other possible cost-effective techniques.For example, a modified fabrication process is implemented to utilize asingle layer stack to fabricate smaller capacitors. For example, FIG. 13illustrates an embodiment of a small macroscopic capacitor 800comprising a 25 μm thick aluminum foil 802 etched on one side to obtain×100 area enhancement, a 20 nm thick Al₂O₃ dielectric layer 804 formedover the etched side 803 of foil 802 either by oxidation, ALD, oroxidation followed by ALD, a 5 nm thick TiN contact layer 806 serving asan adhesion/barrier layer for copper metallization, a 0.5 μm thickcopper layer 858 deposited by first depositing an ALD seed (10 nm)followed by electroplating, and a 2 μm thick copper foil 808 brazed tocopper layer 858 using brazing alloy 852. In this figure, the finercross-hatching at 803 represents the penetration of the etch into thesurface. The large porosity on the etched surface 803 which, incombination with the conformal Al₂O₃ and the conformal ALD deposition ofthe TiN and copper, gives rise to the enhanced capacitance, is not shownas it is much out of scale for the drawing. Alternatively, the entirethickness of 2.5 μm of copper (858+808) is electroplated, eliminatingthe need for brazing alloy 852. Alternatively, layer 808 is depositedusing sputtering techniques eliminating the need for brazing alloy 852.Thin layers of gold, 840 and 842, approximately 50 nm thick, are alsoevaporated over the bottom face of foil 802 and the top face of foil808, respectively, to improve subsequent solder attachment of thecompleted capacitor. Accordingly, 10V compatible capacitors (50%derated) are formed with 35 μF/cm² capacitance and ˜10⁻⁴ Ω/μF ESR. Forexample, using an area of 4×4 mm×mm, a capacitor with 5.6 μF and ESR of˜0.0005Ω is obtained. These capacitors are subsequently brazed orsoldered onto ribbon leads 845 using, for example, brazing alloy 846 andfurther encapsulated with a protective jacket 847 as illustrated in FIG.13 to fabricate discrete (shown) or arrays (not shown) of surface mountcapacitors. Alternatively, foil stacks including layers (from bottom up)840, 802, 804, 806, 858, 808, 842 are integrated into multilayer PCboards (PCB) as described below to advantageously achieve ˜100 μFV/cm³specific capacitance within a thickness of only ˜30 μm.

D. Integration with PC Boards

The capacitor foils represented in the description of embodiments inreference with FIG. 13 above are particularly useful for integrationinto printed circuit boards (PCBs). For example, an embodiment of aportion 900 of a PCB is described in reference to FIG. 14. A capacitoris fabricated as described above over a 25 μm aluminum foil 902 etchedon one side 903. Dielectric layer 904 is grown over the etched side 903,for example, to a thickness of 20 nm that enables 10V applications (at50% derating) grown by ALD or a combination of anodic oxidation and ALD.A contact layer 906 is grown by ALD, for example, 10 nm of TiN. Anadditional layer 958 is grown over layer 906 to obtain low contact ESR,such as 0.5 μm of copper grown by a combination of seed ALD andelectroplating. Both the bottom of foil 902 and top of layer 958 arecoated with PVD gold 940 and 942, respectively, preferably to athickness of 20 nm to 50 nm. This stacked foil 950 is utilized by PCBmanufacturers to integrate capacitors into the layout of PCBs.

For example, in the embodiment illustrated in FIG. 14, metallized Kaptonfilms are implemented to construct multilayer PCBs as known to those whoare skilled in the art. One of the Kapton foils 952 is fabricated with alayout of conductors as known in the art and schematically shown by 947in FIG. 14 and with additional capacitor contact pads 951. Followingthis, foil 950 is laminated and soldered, brazed, or otherwise gluedwith conductive material over Kapton foil 952 with patterned conductors947 and 951. At this point, foil 950 is patterned as known in the artand etched to create the desired capacitors over pads 951. The values ofthe capacitors are selected by selecting the area of the capacitors.Following patterning, subsequent debris removal is performed, as knownin the art. The capacitors with a thickness of ˜26 μm are then soldered,brazed, or glued with conductive cement to pads 948 that are prepared atthe bottom of Kapton foil 954. FIG. 14 does not represent the thicknessvalues of the various layers accurately. Given the significantly smallerthickness of the capacitors at ˜26 μm compared to the final thickness ofthe PCB in the range of 500 μm, the gaps between the capacitors are leftempty in one preferred embodiment. In another preferred embodiment ofthe invention (not shown), the gap is filled with, for example,polyimide of perfluoro-polymer materials. Following the lamination ofKapton foils 952 and 954 together with other foils that comprise thePCB, the capacitors are entirely embedded within the PCB representing asignificant area saving and low contact ESR from pads 951 and 948 tocapacitors electrode 902 and 906, respectively. The method forintegrating foil 950 is compatible with PCB manufacturing techniques andis easily adapted into customized PCB by the pattern of pads 951 and 948and the pattern delineated from foil 950. Typically (although notnecessary), one of the contacts to the capacitors, for example 948, is acontinuous ground plane that covers the majority of the area of therelated Kapton foil, for example 954. Within the delineation of foilstack 950 into the specific pattern, a multiple etch step process isimplemented to adequately etch the various different layers comprisingthe stack.

E. High-Energy Density Capacitor Storage Devices

An objective of this invention is to fabricate high-energy storagecapacitors. Advantageously, capacitors that are suitable for highvoltage are fabricated over aluminum foils with lower area enhancementfoil. For example, 50 μm foils with an etched ×40 area enhancement canaccommodate a 1.0 μm thick Al₂O₃ dielectric layer grown on both sides ofthe foil by ALD or combination of anodic-oxidation and ALD as describedabove. Derated at 50%, these dielectric films are suitable for thefabrication of 500V capacitors. Low ESR contact is established, forexample, by implementing a 50 nm TiN contact layer deposited by ALDfollowed by 0.5 μm of copper deposited by a combination of 10 nm seedALD layer and electroplating and by utilizing a commercially available5.8 μm thick aluminum foil 208 (FIG. 2). Accordingly, capacitance perarea is 0.56 μF/cm². The thickness of the stack is ˜56 μm and the weightper area is 0.01 gram/cm². A capacitor with 400 μF is formed by winding1 cm wide strips. The total area of a strip is 714 cm²; therefore, thelength of a strip is 714 cm. Wound over a stainless thin-wall steelcapillary with 0.3125 cm (⅛ inch) outer diameter, the final capacitorhas a tubular shape with 176 windings, 2.3 cm diameter of wound filmsand 3.4 μΩ ESR, and a weight of 6.7 grams including 2×0.5 mm thickcopper contact discs 270′ and 272′ (FIG. 9) and further illustrated inembodiment 1000 depicted in FIG. 15 a. In FIG. 15 a, the wound capacitorfoil 1010 is shown prior to assembly with contact plates 1020 and 1030.Four capacitors are used to fabricate embodiment 1050 illustrated inFIG. 15 b. The capacitors are assembled in series by soldering orbrazing plates 1020 and 1030 together and then contact pads 1035 and1036 are added. Finally, protective jacket 1040 is fabricated. Thestacked capacitor device having 100 μF capacitance can work at 2 KVvoltage and has an ESR of 13.6 μΩ. A protective and electricallyinsulating jacket 1040 increases the diameter of the complete capacitorto 2.5 cm and the total length to 4.6 cm and adds ˜8 grams to theweight. Accordingly, the complete capacitor weighs ˜35 grams and has avolume of ˜22.6 cm³. Energy storage capacity is shown as E=CV²/2=200jouls or energy density of 5.7 jouls/grams. The capacitor internaldischarge time, τ=RC, is ˜1.4 nsec, suitable for very high peakcurrents. For example, the capacitor holds a charge of ˜0.2 joul whenfully charged at 2 KV and is capable of discharging 50% of that chargewithin ˜1 nsec, providing ˜100,000,000 A of current over a shortcircuit. These properties, together with the long lifetime and hightemperature endurance, represent significant improvements to the priorart.

The descriptions and examples of the preferred embodiment furtherexplain the principles of the invention and are not meant to limit thescope of invention to any specific method or apparatus. All suitablemodifications, implementations, and equivalents are included in thescope of the invention as defined by the summary of the invention andthe following claims:

1. A capacitor including a chemically etched metallic foil, said capacitor comprising: a conformal and substantially uniform dielectric layer grown over said metallic foil; and a substantially uniform and conformal conductive film grown on said dielectric layer.
 2. The capacitor of claim 1 wherein an additional metal foil is in substantial electrical contact with a portion of said conformal conductive film.
 3. The capacitor of claim 1 wherein at least a portion of said conformal conductive film is grown by ALD.
 4. The capacitor of claim 1, further comprising an additional conductive layer in substantial electrical contact with said conformal conductive film.
 5. The capacitor of claim 4 further comprising an additional metal foil in substantial electrical contact with a portion of said additional conductive film. 6-8. (canceled)
 9. The capacitor of claim 2 comprising: a capacitor core stack comprising: a first metal foil; and a repeatable stack; said repeatable stack comprises a selected number of foil pairs; and said foil pairs comprise: said capacitor foil; and said additional metal foil.
 10. The capacitor of claim 5 comprising: a capacitor core stack comprising: a first metal foil; and a repeatable stack; said repeatable stack comprises a selected number of foil pairs; and said foil pairs comprise: said capacitor foil; and said additional metal foil.
 11. The capacitor of claim 4 comprising: a capacitor core stack comprising a repeatable stack; and said repeatable stack comprises a selected number of said capacitor foils.
 12. The capacitor of claim 9 wherein electrical contacts formed on planar faces of said capacitor core stack, and said electrical contacts comprise: a first insulation over an edge of said additional metal foil on a first face; a first electrical contact with the edge of said additional metal foil formed on the first face; a second insulation over the edge of said additional metal foil on a second face; and a second electrical contact with the edge of said additional metal foil formed on the second face. 13-14. (canceled)
 15. The capacitor of claim 9 wherein said capacitor core stack is cut into capacitor core pieces; and electrical contacts formed on two parallel sides of said capacitor core pieces; and said electrical contacts comprise: a first insulation over an edge of said additional metal foil on the first side; a first electrical contact with the edge of said metal foil formed on the first side; a second insulation over the edge of said metal foil on a second side; and a second electrical contact with the edge of said additional metal foil formed on the second side.
 16. The capacitor of claim 10 wherein said capacitor core stack is cut into capacitor core pieces; and electrical contacts formed on two parallel sides of said capacitor core pieces; and said electrical contacts comprise: a first insulation over an edge of said additional metal foil on a first side; a first electrical contact with the edge of said metal foil formed on the first side; a second insulation over the edge of said metal foil on a second side; and a second electrical contact with the edge of said additional metal foil formed on the second side.
 17. The capacitor of claim 11 wherein said capacitor core stack is cut into capacitor core pieces; and electrical contacts formed on two parallel sides of said capacitor core pieces; and said electrical contacts comprise: a first insulation over an edge of said additional conductive layer on a first side; a first electrical contact with the edge of said metal foil formed on the first side; a second insulation over the edge of said metal foil on a second side; and a second electrical contact with the edge of said additional conductive layer formed on the second side.
 18. The capacitor of claim 1 wherein at least a portion of said dielectric layer is formed by ALD.
 19. The capacitor of claim 1 wherein at least a portion of said dielectric layer is formed by anodic oxidation.
 20. The capacitor of claim 18 wherein a portion of said dielectric layer is formed by anodic oxidation; a portion of said dielectric layer is formed by ALD; and the thickness of said ALD portion is selected to substantially increase the breakdown voltage of said dielectric layer.
 21. The capacitor of claim 1 wherein said capacitor foil is electrically biased; and said electrically biased comprises: applying electrical potential between said metal foil and said conformal conductive film; said electrical potential is selected to increase the breakdown voltage of said dielectric layer; and the capacitance of said capacitor is substantially maintained.
 22. The capacitor of claim 1 wherein said capacitor foil is electrically biased; and said electrically biased comprises: applying electrical potential between said metal foil and said conformal conductive film; said electrical potential is selected to reduce the leakage current through said dielectric layer; and the capacitance of said capacitor is substantially maintained.
 23. The capacitor of claim 1 wherein said dielectric layer is electrically biased; and said electrically biased comprises: applying electrical potential between said metal foil and an electrolyte; said electrolyte provides electrical contact with said dielectric layer; said electrical potential is selected to increase the breakdown voltage of said dielectric layer; and the thickness of said dielectric layer is not substantially increased.
 24. The capacitor of claim 1 wherein said capacitor foil is mounted onto a PCB; and said PCB comprises: electrical contact pads; said mounting comprises substantially making low ESR electrical contact with said electrical contact pads; said capacitor foil is delineated to define capacitors; said defined capacitors comprise of selected capacitance; and said selected capacitance is determined by the capacitance per area of said capacitor foil and the area of said defined capacitors.
 25. The capacitor of claim 4 wherein said capacitor foil is mounted onto a PCB; said PCB comprises electrical contact pads; said mounting comprises substantially making low ESR electrical contact with said electrical contact pads; said capacitor foil is delineated to define capacitors; said defined capacitors comprise of selected capacitance; and said selected capacitance is determined by the capacitance per area of said capacitor foil and the area of said defined capacitors.
 26. The capacitor of claim 1 wherein said metal foil comprises aluminum.
 27. The capacitor of claim 1 wherein said dielectric layer comprises aluminum oxide.
 28. The capacitor of claim 1 wherein said conformal conductive film comprises titanium nitride.
 29. The capacitor of claim 1 wherein said high area comprises more than 10 times area enhancement.
 30. The capacitor of claim 1 wherein said capacitor foil comprises: said high area on both sides; said dielectric layer is grown on both sides of said metal foil; and said conformal conductive film is grown on said dielectric layer on both sides of said capacitor foil.
 31. A capacitor fabrication method comprising providing a conductive foil having an irregular surface to augment its area and oxidizing the surface area of said conductive foil to form a dielectric film, said method comprising: conformally growing a conductive film onto said dielectric film to form a capacitor foil; and completing said capacitor to include said capacitor foil.
 32. (canceled)
 33. The capacitor fabrication method as in claim 31 comprising: stacking said capacitor foil into a capacitor core stack; cutting said capacitor core stack into capacitor core pieces; selecting two parallel sides on said capacitor core pieces; electrically contacting the edge of said high area metal foil on said first side; and electrically contacting the edge of said conductive film on said second side.
 34. A method of making a macroscopic capacitor comprising providing a substrate having a large surface area, said method comprising: forming a conformal layer of either a dielectric or a conductor over said substrate using atomic layer deposition; and completing said macroscopic capacitor to include said conformal layer.
 35. A method as in claim 34 wherein said forming comprises forming a dielectric material.
 36. A method as in claim 34 wherein said dielectric material is selected from the group consisting of Al₂O₃, an oxide of silicon, Ta₂O₅, HfO₂, ZrO₂, TiO₂, and combinations thereof.
 37. A method as in claim 34 wherein said forming comprises forming a conductor.
 38. A method as in claim 37 wherein said conductor is selected from the group consisting of Ti N, copper, tungsten, ruthenium, and combinations thereof.
 39. A method of claim 34 wherein said completing comprises completing a discrete electrical component, a hybrid electrical component, or a portion of a printed circuit board. 